Traditional receiver circuits for dual data rate (DDR) dynamic random access memory (DRAM) devices typically operate at a fixed DC common mode of 0.5 times GVDD, where GVDD is the DDR IO (input/output) supply voltage level defined by the DDR interface specification. This fixed DC common mode has been used for DDR1-DDR3 protocols. To enhance the power performance of DDR interfaces, however, the DDR4 specification terminates the data lines at GVDD instead of GVDD/2. As such, the DC common mode for the data lines is shifted towards 0.75 times GVDD with the upper end for the DC common mode being about 0.92 times GVDD. At the same time, the low end for the DC common mode is shifted down to about 0.45 times GVDD. In addition to this expanded range for DC common mode levels, the high-to-low voltage swings for the data signals within the DDR4 specification can range from 0.08 times GVDD to about 0.8 times GVDD. These new DDR4 interface specifications can lead to combinations that create significant detection problems for standard differential data receivers. One such combination is where a relatively low high-to-low data swing such as 0.08 times GVDD is used in combination with a relatively high DC common mode such as 0.92 times GVDD. And at the other extreme is a relatively high data swing such as 0.8 times GVDD in combination with a relatively low DC common mode such as 0.45 times GVDD.
FIG. 7 (Prior Art) provides a voltage level signal diagram 700 that represents the two extreme conditions set forth above. A first input signal (INPUT 1) 702 represents the first example above, and a second input signal (INPUT 2) represents the second example above. The DC common mode variation 706 ranges from 0.92 times GVDD to 0.45 GVDD, and the signal voltage swings vary from 0.08 times GVDD to 0.8 times GVDD. Other DC common mode voltages levels and signals swings can also be used between these extremes according to the DDR4 interface specification.